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description the CXP750064/750072/750080 are the cmos 8-bit single chip microcomputer integrating on a single chip an a/d converter, serial interface, timer/counter, time- base timer, on-screen display function, i 2 c bus interface, pwm output, remote control reception circuit, hsync counter, watchdog timer, 32khz timer/counter besides the basic configurations of 8-bit cpu, rom, ram, i/o ports. the CXP750064/750072/750080 also provide a sleep function that enables to lower the power consumption. features a wide instruction set (213 instructions) which covers various types of data ?16-bit operation/multiplication and division/ boolean bit operation instructions minimum instruction cycle 167ns at 24mhz operation 122s at 32khz operation incorporated rom 64k bytes (CXP750064) 72k bytes (cxp750072) 80k bytes (cxp750080) incorporated ram 1984 bytes (excludes vram for on-screen display) peripheral functions ?a/d converter 8-bit 6-channel successive approximation method (conversion time of 3.25s at 16mhz) ?serial interface 8-bit clock sync type, 1 channel ?timer 8-bit timer 8-bit timer/counter 19-bit time-base timer 32 khz timer/counter ?on-screen display (osd) function 24 32 dots, 512 character types, 15 character colors, 2 lines 32 characters, frame background 8 colors/ half blanking, background on full screen 15 colors/ half blanking edging/ shadowing/ rounding for every line, background with shadow for every character, double scanning, sprite osd, 24 32 dots, 1 screen, 8 colors for every dot ?i 2 c bus interface ?pwm output 8 bits, 8 channels 14 bits, 1 channel ?remote control reception circuit 8-bit pulse measurement counter, 6-stage fifo ?hsync counter 2 channels ?watchdog timer interruption 13 factors, 13 vectors, multi-interruption possible standby mode sleep package 64-pin plastic sdip/qfp piggyback/evaluator cxp750000 64-pin ceramic pqfp/psdip (supports custom font) perchase of sony's i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips. CXP750064/750072/750080 cmos 8-bit single chip microcomputer ?1 e02939-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin sdip (plastic) 64 pin qfp (plastic) structure silicon gate cmos ic
?2 CXP750064/750072/750080 a/d converter 6ch fifo remocon serial interface unit 8-bit timer 1 8-bit timer/ counter 0 on screen display hsync counter 0 hsync counter 1 i 2 c bus interface unit 8 bits pwm 8ch (6ch) 14 bits pwm 1ch prescaler/ time-base timer watchdog timer 32khz timer/counter rom 64k/72k/80k bytes ram 1984 bytes spc700 cpu core clock generator /system control interrupt controller port a port b port c port d port e port f port g pg3 to pg6, pg7 pwm 5 pf0 to pf7 8 pe4 to pe6 3 pe2, pe3 2 pe0, pe1 2 pd0 to pd7 8 pc6, pc7 2 pc0 to pc5 6 pb0 to pb7 8 pa0 to pa7 8 pwm0 to pwm7 adj scl1 scl0 sda1 sda0 hs1 hs0 vsync hsync ym ys i b g r exlc xlc to ec sck so si rmc an0 to an5 6 2 2 2 int0 int1 int2 tex tx extal xtal v dd v ss rst 8 block diagram
3 CXP750064/750072/750080 40 39 38 37 36 35 34 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 31 32 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 v ss v dd nc exlc xlc pe4/ym pe5/ys pe6/i b g r pb0 pb1 pb2 pg3 pg4 pc4 pc5 pc6/pwm6 pc7/pwm7 pf0/pwm0 pf1/pwm1 pf2/pwm2 pf3/pwm3 pf4/scl0 pf5/scl1/pwm4 pf6/sda0 pf7/sda1/pwm5 pe0/to/adj pe1/pwm pe2/tex/int0 pe3/tx hs0/pd4 pc3 pc2 pc1 pc0 ec/pd7 rmc/pd6 hs1/pd5 si/pd3 so/pd2 sck/pd1 int2/pd0 hsync/pa7 vsync/pa6 rst v ss pa0/an0 xtal extal pa5/an5 pa4/an4 pa3/an3 pa2/an2 pa1/an1 pb7 pb6 pb5 pb4 pb3 int1/pg7 pg6 pg5 pin assignment (top view) 64-pin sdip note) 1. nc (pin 46) is left open. 2. vss (pins 16 and 48) are both connected to gnd.
4 CXP750064/750072/750080 v ss v dd nc exlc xlc pe4/ym pe5/ys pe6/i b g pe1/pwm pe2/tex/int0 pe3/tx pf3/pwm3 pf4/scl0 pf5/scl1/pwm4 pf6/sda0 pf7/sda1/pwm5 pe0/to/adj 40 39 38 37 36 35 34 33 41 42 43 44 45 46 47 48 49 50 51 pf2/pwm2 pf1/pwm1 pf0/pwm0 pc7/pwm7 pc6/pwm6 pc5 pc4 pc3 pc2 pc1 pc0 pd7/ec pd6/rmc 52 53 54 55 56 57 58 59 60 63 64 61 62 r pb0 pb1 pb2 pg3 pg4 pg5 pg6 int1/pg7 pb3 pb4 pb5 pb6 31 32 20 21 22 23 24 25 26 27 28 29 30 hs0/pd4 hs1/pd5 si/pd3 so/pd2 sck/pd1 int2/pd0 hsync/pa7 vsync/pa6 rst v ss pa0/an0 xtal extal pa5/an5 pa4/an4 pa3/an3 pa2/an2 pa1/an1 pb7 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 pin assignment (top view) 64-pin qfp note) 1. nc (pin 40) is left open. 2. vss (pins 10 and 42) are both connected to gnd.
5 CXP750064/750072/750080 (port a) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port b) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port c) lower 6 bits are i/o ports; i/o can be set in a unit of single bits. upper 2 bits are output port and large current (12ma) n-channel open drain output. upper 2 bits are medium drive voltage (12v); lower 6 bits are 5v drive. (8 pins) (port d) 8-bit i/o port. i/o can be set in a unit of single bits. can drive 12ma synk current. (8 pins) (port e) bits 0 and 1 are i/o port; i/o can be set in a unit of single. bits 2 and 3 are input port. bits 4, 5 and 6 are output port. (7 pins) pin description symbol pa0/an0 to pa5/an5 pa6/vsync pa7/hsync pb0 to pb7 pc0 to pc5 pc6/pwm6 to pc7/pwm7 pd0/int2 pd1/sck pd2/so pd3/si pd4/hs0 pd5/hs1 pd6/rmc pd7/ec pe0/to/adj pe1/pwm pe2/tex/int0 pe3/tx pe4/ym pe5/ys pe6/i b g r i/o/ analog input i/o/input i/o/input i/o i/o output/output i/o/input i/o/i/o i/o/output i/o/input i/o/input i/o/input i/o/input i/o/input i/o/output/ output i/o/output input/input/ input input/output output/output output/output output/output output output output i/o description analog inputs to a/d converter. (6 pins) osd display vertical sync signal input. osd display horizontal sync signal input. 8-bit pwm output. (2 pins) external interruption request input. active at the falling edge. serial clock i/o. serial data output. serial data input. hsync counter (ch0) input. hsync counter (ch1) input. remote control reception circuit input. external event input for timer/counter. rectangular wave output for 8-bit timer/counter. 14-bit pwm output. connects a crystal for 32khz timer/counter clock oscillation. when used as an event counter, input to tex pin and leave tx pin open. tex oscillation frequency dividing output. external interruption request input. active at the falling edge. osd display 6-bit output. (6 pins)
6 CXP750064/750072/750080 (port f) 8-bit output port and large current (12ma) n-channel open drain output. lower 4 bits are medium drive voltage (12v); upper 4 bits are 5v drive. (8 pins) (port g) 5-bit i/o port. i/o can be set in a unit of single bits. (5 pins) connects a crystal for system clock oscillation. when a clock is supplied externally, input to extal pin and input a reversed phase clock to xtal pin. system reset; active at low level. osd display clock oscillation i/o. oscillation frequency is determined by the external l and c. no connected. positive power supply. gnd. connect two vss pins to gnd. 8-bit pwm output. (4 pins) i 2 c bus interface transfer clock i/o. (2 pins) i 2 c bus interface transfer data i/o. (2 pins) symbol pf0/pwm0 to pf3/pwm3 pf4/scl0 pf5/scl1/ pwm4 pf6/sda0 pf7/sda1/ pwm5 pg3 to pg6 pg7/int1 extal xtal rst exlc xlc nc v dd vss output/output output/i/o output/i/o/ output output/i/o output/i/o/ output i/o i/o/input input output input input output i/o description 8-bit pwm output. 8-bit pwm output. external interruption request input. active at the falling edge.
7 CXP750064/750072/750080 port a data port a direction ip rd (port a) internal data bus 0 after a reset port a function selection 0 after a reset a/d converter input multiplexer input protection circuit port a data port a direction ip input polarity rd (port a) internal data bus hsync, vsync 0 after a reset 0 after a reset schmitt input ports b, c, g data ports b, c, g direction ip rd (ports b, c, g) internal data bus int1 0 after a reset pb0 to pb2 schmitt input only for pg7 input/output circuit formats for pins port a port a port b port c 6 pins 2 pins 19 pins hi-z hi-z hi-z pin after a reset circuit format pa6/vsync pa7/hsync pb0 to pb7 pc0 to pc5 pg3 to pg6 pg7/int1 pa0/an0 to pa5/an5 port g ports c and f data ports c and f function selection 0 after a reset 1 after a reset pwm0 to pwm3 pwm6, pwm7 ? 1 12v drive voltage large current 12ma ? 1 rd (ports c, f) internal data bus port c 6 pins pc6/pwm6 pc7/pwm7 pf0/pwm0 to pf3/pwm3 hi-z port f
8 CXP750064/750072/750080 port d data port d direction ip rd (port d) internal data bus int2, si, hs0, hs1, rmc, ec 0 after a reset schmitt input ? large current 12ma ? port d data port d direction ip rd (port d) internal data bus 0 after a reset schmitt input only for pd1 sck, so sio output enable sck only ? large current 12ma ? port e data 1 after a reset to adj16k ? 1 adj2k ? 1 01 00 10 11 mpx internal data bus port e direction 1 after a reset port e function selection (lower) 00 after a reset ip port e function selection (upper) internal reset signal ? 2 ? 1 adj signals are frequency dividing outputs for 32khz oscillation frequency adjustment. adj2k provides usage as buzzer output. ? 2 pull-up resistors approx. 150k ? rd (port e) port d port d port e 6 pins 2 pins 1 pin hi-z hi-z high level h level at on resistance of pull-up transistor during a reset pin after a reset circuit format pd1/sck pd2/so pe0/to/adj pd0/int2 pd3/si pd4/hs0 pd5/hs1 pd6/rmc pd7/ec ()
9 CXP750064/750072/750080 ip ip tex oscillation circuit control rd (port e) schmitt input schmitt input clock input internal data bus intrenal data bus int0 1 after a reset pe2/ tex/ int0 pe3/ tx rd (port e) port e data port e direction ip rd (port e) internal data bus 1 after a reset pwm 1 after a reset port e function selection 0 after a reset port e port e 1 pin 2 pins 3 pins pin after a reset circuit format pe2/tex/int0 pe3/tx high level oscillation halted port input hi-z pe1/pwm pe4/ym pe5/ys pe6/i ym, ys, i output polarity 0 after a reset port e function selection 1 after a reset port e data internal data bus rd (port e) writing data to output polarity register and port data register brings output to active. port e
10 CXP750064/750072/750080 4 pins 3 pins pin after a reset circuit format r g b hi-z hi-z i 2 c bus enable port f data port f function selection 0 after a reset 1 after a reset pwm4, pwm5 scl, sda scl, sda (i 2 c bus circuit) ip schmitt input ? large current 12ma to internal i 2 c pins (scl1 for scl0) bus sw ? rd (port f) internal data bus r, g, b output polarity 0 after a reset writing data to output polarity register brings output to active. port f pf4/scl0 pf5/scl1/pwm4 pf6/sda0 pf7/sda1/pwm5 exlc xlc ip oscillation control ip osd display clock ip extal xtal diagram shows the circuit composition during oscillation. feedback resistor is removed and xtal is driven at h level driving stop. (this device does not enter the stop mode.) aa aa schmitt input pull-up resistor op mask option 2 pins exlc xlc 2 pins extal xtal 1 pin rst oscillation halted oscillation low level (during a reset)
11 CXP750064/750072/750080 ? 1 v in and v out should not exceed v dd + 0.3v. ? 2 the large current output port is port c (pc6, pc7), port d (pd) and port f (pf). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding those conditions may adversely affect the reliability of the lsi. v dd v in v out v outp i oh i oh i ol i olc i ol topr tstg p d 0.3 to +7.0 0.3 to +7.0 ? 1 0.3 to +7.0 ? 1 0.3 to +15.0 5 50 15 20 130 20 to +75 55 to +150 1000 600 v v v v ma ma ma ma ma c c mw mw total of all output pins ports excluding large current output (value per pin) large current output ports (value per pin ? 2 ) total of all output pins sdip-64p-01 qfp-64p-l01 item symbol ratings unit remarks absolute maximum ratings (vss = 0v reference) supply voltage input voltage output voltage medium drive output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation
12 CXP750064/750072/750080 supply voltage high level input voltage low level input voltage operating temperature 5.5 5.5 5.5 v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v v v v v c item symbol min. max. unit remarks 4.5 3.5 2.7 0.7v dd 0.8v dd v dd 0.4 0 0 0.3 20 v ih v ihs v ihex v il v ils v ilex topr guaranteed operation range for 1/2 and 1/4 frequency dividing modes guaranteed operation range for 1/16 frequency dividing mode or sleep guaranteed operation range for tex mode guaranteed data hold range for stop ? 5 ? 1 ? 2 extal pin ? 3 , tex pin ? 4 ? 1 ? 2 extal pin ? 3 , tex pin ? 4 v dd ? 1 this device does not enter the stop mode. ? 2 pa0 to pa5, pb3 to pb7, pc0 to pc5, pd2, pe0, pe1, pe3, pg3 to pg6, scl0, scl1, sda0, sda1 pins ? 3 vsync, hsync, int2, sck, si, hs0, hs1, rmc, ec, int0, int1, rst pins ? 4 specifies only during external clock input. ? 5 specifies only during external event count input. recommended operating conditions (vss = 0v reference)
13 CXP750064/750072/750080 v dd = 4.5v, i oh = 0.5ma v dd = 4.5v, i oh = 1.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 3.0ma v dd = 4.5v, i ol = 4.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v v dd = 4.5v, i ol = 12.0ma high level output voltage low level output voltage input current i/o leakage current open drain i/o leakage current (in n-ch tr off state) supply current ? 2 4.0 3.5 20 33 2.2 12 a ma a a 50 10 120 30 29 45 82 3.8 35 ma a a ? 0.4 0.6 1.5 0.4 0.6 40 40 10 10 400 10 v v v v v a a a a a a 0.5 0.5 0.1 0.1 1.5 v v pa, pb, pc0 to pc5, pd, pe0 to pe1, pe4 to pe6, pg, r, g, b pa to pd, pe0 to pe1, pe4 to pe6, pf0 to pf3, pg, r, g, b pc6, pc7, pd, pf pf4 to pf7 (scl0, scl1, sda0, sda1) extal rst ? 1 pa, pb, pc0 to pc5,pd, pe, pg, r, g, b, rst ? 1 pc6, pc7, pf0 to pf3 pf4 to pf7 scl0: scl1 sda0: sda1 v dd = 5.5v, v il = 0.4v v dd = 5.5v, v i = 0, 5.5v v dd = 5.5v, v oh = 12.0v v dd = 5.5v, v oh = 5.5v v dd = 4.5v v scl0 = v scl1 = 2.25v v sda0 = v sda1 = 2.25v v dd v dd = 3.3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) item symbol pins conditions min. typ. max. unit v oh v ol i iz i loh r bs i dd1 i dd2 i dds1 i dds2 i dds3 i ihe i ile i iht i ilt i ilr electrical characteristics dc characteristics (ta = 20 to +75 c, vss = 0v reference) 1/2 frequency dividing mode tex v dd = 5.5v, 16mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 5.5v, 24mhz crystal oscillation v dd = 3.3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) sleep mode v dd = 5.5v, 24mhz crystal oscillation (c 1 = c 2 = 15pf) stop mode ? 3 v dd = 5.5v, termination of 24mhz and 32khz oscillation i 2 c bus switch connection impedance (in output tr off state)
14 CXP750064/750072/750080 ? 1 for rst pin, specifies the input current when pull-up resistance is selected, and specifies the leakage current when non-resistor is selected. ? 2 when all output pins are left open. specifies only when the osd oscillation is halted. ? 3 this device does not enter the stop mode. input capacitance 10 20 pf pa, pb,pc0 to pc5, pd,pe0 to pe3, pf4 to pf7, pg, extal, exlc, rst clock 1 mhz 0v other than the measured pins item symbol pins conditions min. typ. max. unit c in
15 CXP750064/750072/750080 ? 1 indicates three values according to the contents of the clock control register (clc: 000feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = 00 ), 4000/fc (upper 2 bits = 01 ), 16000/fc (upper 2 bits = 11 ) extal t xh t xl t cf t cr 0.4v v dd 0.4v 1/fc aaaaa a aaa a aaaaa aaaa a aa a aaaa crystal oscillation ceramic oscillation extal xtal external clock extal xtal 74hc04 c 1 c 2 aaaa a aa a aaaa 32khz clock applied condition crystal oscillation tex tx c 1 c 2 tex ec t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise and fall times event count input clock pulse width event count input clock rise and fall times system clock frequency event count input clock input pulse width event count input clock rise and fall times f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal extal extal ec ec tex tx tex tex mhz ns ns ns ms khz s ms item symbol pins conditions min. unit fig. 1, fig.2 fig. 1, fig.2 external clock drive fig. 1, fig.2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5 v fig. 2 (32khz clock applied conditions) fig. 3 fig. 3 8 17 4 t sys ? 1 10 typ. 32.768 max 24 200 20 20 (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) fig.2. clock applied conditions fig. 1. clock timing fig. 3. event count clock timing
16 CXP750064/750072/750080 0.2v dd 0.8v dd t kl t kh so t kcy t sik t ksi 0.2v dd 0.8v dd t kso 0.2v dd 0.8v dd output data input data si sck (2) serial transfer (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item sck cycle time t kcy sck input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc 50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns sck si si so t kh t kl t sik t ksi t kso sck high and low level width si input setup time (for sck ) si hold time (for sck ) sck so delay time symbol pins conditions min. max. unit note) the load of sck output mode and so output delay time is 50pf + 1ttl. fig. 4. serial transfer timing
17 CXP750064/750072/750080 resolution linearity error zero transition voltage full-scale transition voltage conversion time sampling time analog input voltage v zt ? 1 v ft ? 2 t conv t samp v ian an0 to an5 ta = 25 c v dd = 5.0v vss = 0v 10 4910 26/f adc ? 3 6/f adc ? 3 0 10 4970 8 3 70 5030 v dd bits lsb mv mv s s v item symbol pins conditions min. typ. max. unit (3) a/d converter (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) linearity error v zt v ft analog input ffh feh 01h 00h digital conversion value fig. 5. definitions for a/d converter terms ? 1 v zt : value at which the digital conversion value changes from 00h to 01h and vice versa. ? 2 v ft : value at which the digital conversion value changes from feh to ffh and vice versa. ? 3 f adc indicates the below values due to the contents of bit 6 (cks) of the a/d control register (adc: 000f6h): f adc = fc (cks = 0 ), fc/2 (cks = 1 )
18 CXP750064/750072/750080 external interruption high, low level width reset input low level width int0 int1 int2 rst 1 32/fc s s item symbol pins conditions min. max. unit t ih t il t rsl (4) interruption, reset input (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) 0.2v dd 0.8v dd t ih t il int0 int1 int2 (falling edge) fig. 6. interruption input timing t rsl 0.2v dd rst fig. 7. rst input timing
19 CXP750064/750072/750080 (5) i 2 c bus timing (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item scl clock frequency bus-free time before starting transfer hold time for starting transfer clock low level width clock high level width setup time for repeated transfers data hold time data setup time sda, scl rise time sda, scl fall time setup time for transfer completion f slc t buf t hd; sta t low t high t su; sta t hd; dat t su; dat t r t f t su; sto scl sda, scl sda, scl scl scl sda, scl sda, scl sda, scl sda, scl sda, scl sda, scl 0 4.7 4.0 4.7 4.0 4.7 0 ? 1 250 4.7 100 1 300 khz s s s s s s ns s ns s symbol pins conditions min. max. unit ? 1 the data hold time should be 300ns or more because the scl rise time (300ns max.) is not included in it. fig. 8. i 2 c bus transfer timing p st t su ; sto t su ; sta t hd ; sta t su ; dat t high t hd ; dat t f t r t low t hd ; sta s p t buf sda scl fig. 9. i 2 c bus device recommended circuit i 2 c bus device i 2 c bus device r s r s r s r s r p r p sda0 (or sda1) scl0 (or scl1) a pull-up resistor (rp) must be connected to sda0 (or sda1) and scl0 (or scl1). the sda0 (or sda1) and scl0 (or scl1) series resistance (rs = 300 ? or less) can be used to reduce the spike noise caused by crt flashover.
20 CXP750064/750072/750080 l c 2 c 1 exlc xlc r ? 3 (6) osd timing (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item osd clock frequency hsync pulse width vsync pulse width hsync afterwrite rise and fall times vsync beforewrite rise and fall times f osc t hwd t vwd t hcg t vcg exlc xlc hsync vsync hsync vsync fig. 11 fig. 10 fig. 10 fig. 10 fig. 10 4 30/fc 1 40.8 200 1.0 mhz s h ? 2 ns s symbol pins conditions unit min. max fig. 10. osd timing 0.8v dd 0.2v dd t hcg t hwd hsync for osd i/o polarity register (opol: 001feh) bit 7 at 0 0.8v dd 0.2v dd t vcg vsync for osd i/o polarity register (opol: 001feh) bit 6 at 0 t vwd fig. 11. lc oscillation circuit connection ? 3 the series resistor for xlc (r = 1k ? or less) can reduce the frequency of occurrence of the undesired radiation. ? 1 the maximum value of fosc is specified with the following equation. fosc [max] fc 1.7 ? 2 h indicates 1hsync period.
21 CXP750064/750072/750080 appendix c 2 rd aaaa a aa a aaaa extal xtal c 1 (i) main clock aaaaa a aaa a aaaaa tex tx c 1 c 2 rd (iii) sub clock rd aaaa a aa a aaaa extal xtal c 1 c 2 (ii) main clock a a a a reset pin pull-up resistor non-existent existent item content mask option table ? models with an astarisk ( ? ) have the built-in ground capacitance (c 1 , c 2 ). ? 1 the series resistor for xtal (rd = 500 ? or less) can reduce the effect of the noise caused by the electrostatic discharge. manufacture river eletec co., ltd. murata mfg co., ltd. csa10.0mtz csa12.0mtz csa16.00mxz040 csa24.00mxz040 cst10.0mtw ? cst12.0mtw ? cst16.00mxw0c1 ? kinseki ltd. seiko instruments inc. model hc-49/u03 hc-49/u (-s) p3 fc (mhz) 10.0 12.0 16.0 24.0 10.0 12.0 16.0 8.0 12.0 16.0 8.0 12.0 16.0 24.0 30 5 open 30 5 18 12 10 10 5 open 3 30 18 30 5 open 30 5 18 12 10 10 5 open 3 33 18 0 ? 1 330 ? 1 0 ? 1 120k 32.768khz (iii) vtc-200 sp-t 330k 32.768khz (iii) c 1 (pf) c 2 (pf) rd ( ? ) circuit example remarks (i) (i) (ii) cl = 12.5pf fig. 12. recommended oscillation circuit
22 CXP750064/750072/750080 fig. 13. characteristic curves 3 45 6 0.1 1 7 2 0.01 10 100 100 10 20mhz 24mhz 32mhz 50 100 90 80 70 60 40 30 20 10 0 1 0.1 0.01 28mhz 16mhz 1 0 fc = 24mhz fc = 16mhz fc = 24mhz fc = 16mhz fc = 24mhz fc = 16mhz fc = 24mhz fc = 16mhz 30 15 10 15 05 20 0 25 20 5 25 10 36mhz 40mhz i dd vs. v dd (ta = 25 c, typical) i dd supply current [ma] v dd supply voltage [v] sleep mode 1/2 dividing mode 1/4 dividing mode i dd vs. fc (v dd = 5v, ta = 25 c, typical) 1/16 dividing mode 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode parameter curve for osd oscillator l vs. c (analytically calculated value) l inductance [h] c 1 , c 2 capacitance [pf] frequency [mhz] i dd supply current [ma] 32khz operation mode 32khz sleep mode
23 CXP750064/750072/750080 package outline unit: mm 64pin sdip (plastic) min 0.5 min 3.0 4.75 0.1 0.9 0.15 0.5 0.1 0.25 0.05 + 0.1 17.1 0.1 19.05 132 33 64 1.778 57.6 0.1 + 0.4 package material lead treatment lead material package mass epoxy resin 42/copper alloy sony code eiaj code jedec code sdip-64p-01 p-sdip64-17.1x57.6-1.778 solder plating 8.6g + 0.3 + 0.3 0 to 15 package structure lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec.
24 CXP750064/750072/750080 package outline unit: mm sony code eiaj code jedec code 23.9 0.4 20.0 0.1 0.4 0.1 + 0.15 14.0 0.1 1 19 20 32 33 51 52 64 0.15 0.05 + 0.1 2.75 0.15 16.3 0.1 0.05 + 0.2 0.8 0.2 m 0.2 0.15 + 0.4 17.9 0.4 + 0.4 + 0.35 64pin qfp (plastic) qfp-64p-l01 p-qfp64-14x20-1.0 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 1.5g 1.0 0 to 15 sony corporation lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec.

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